1. Field of the Invention
The invention relates generally to decoding systems and, more particularly, to timing loops used in the decoder to control signal sampling.
2. Background Information
Increases in the storage capacities of hard disks or other storage devices result in read signals with smaller signal-to-noise ratios (SNRs). For better detection and decoding results with the lower SNRs, iterative detection and decoding methods, such as majority a posteriori (MAP) detecting and low-density parity check (LDPC) decoding are used to reproduce recorded data. The iterative methods work well at low raw bit error rates, and thus, the accurate operations of timing loops associated with detecting the bits in the read signals are critical. The timing loop controls the times at which the sampling of the data, or read, signal occurs. In the low SNR environment, the sampling rate must be closely matched to the bit rate of the read signal, to ensure that the decoder is decoding data and not noise.
The disk drives may employ a disk lock clock (DLC) that attenuates the phase or frequency error between a sample timing clock and the recorded signal bit rates. Such clocks are described in U.S. Pat. No. 6,738,205 entitled Self-Writing of Servo Patterns in Disk Drives, which is assigned to a common assignee and incorporated herein by reference. Essentially the DLC utilizes preamble or other information recorded on the disk to match the clock rate to the bit rate used for recording. The timing loop then fine tunes the clock signal to correspond to the bit rate in the read signal. Using the DLC, the timing loop operates with a narrow bandwidth and, even in the low SNR environment, runs without exceeding an acceptable loss of lock rate threshold.
There are, however, certain relatively large timing disturbances that cause the narrow bandwidth timing loop to lose lock at a rate that is unacceptable. Examples of the timing disturbances are phase steps, phase humps, and sinusoidal disturbances. When such a timing disturbance occurs, the system increases the bandwidth of the timing loop, in an attempt to maintain lock to the read signal bit rate. However, in the low SNR environment, the increase in bandwidth and the resulting increase in the noise included in the decoding operations may result ultimately in the failure of the timing loop, and thus, in a failure to properly decode the data.
Various techniques are currently used in an attempt to recover data after an unsuccessful decoding operation. One error recovery technique involves rereading the data block from the hard disk and performing a full detecting and decoding operation using the new read signal. If the first rereading and decoding iteration does not result in a data block that contains a correctable number of errors, the system may reread and decode the block a number of times. In certain drives, attempts are made to improve the SNR in the reread signals by reducing the adverse effects of non-repeatable noise through what is referred to as “ADC sample averaging.” This technique is discussed in U.S. Pat. No. 6,412,088 entitled Method and Apparatus For Using Block Reread, which is assigned to a common assignee and incorporated herein by reference in its entirety.
The ADC sample averaging works well in most error recovery mode operations. However, in operations that involve large timing disturbances, the rereading of the sector is performed with the wider bandwidth timing loop, and the ADC sampling may often occur when the timing loop is operating with a loss of lock. Accordingly, the samples obtained from these rereadings may, if they are included in the averaging, actually add further noise into the error recovery mode operations. Indeed, incorporating these samples may significantly increase the timing jitter of the timing loop.
Accordingly, what is needed is a mechanism that reduces the timing jitter of the wide bandwidth timing loop over multiple rereads of the sector during error recovery mode operations associated with large timing disturbances.